Embodiments of the present invention relate to a semiconductor device, and more particularly to a semiconductor device and a method for forming the same.
Most modern electronic appliances comprise a semiconductor device. A semiconductor device comprises electronic elements such as a transistor, a resistor and a capacitor. These electronic elements are designed to perform partial functions of electronic appliances, and are integrated on a semiconductor substrate. For example, electronic elements such as a computer or a digital camera include a memory chip for storing information and a processing chip for processing information. Memory chips and processing chips include electronic elements integrated on a semiconductor substrate.
Semiconductor devices have a need for a higher degree of integration in order to satisfy consumer demands for superior performance and lower prices. Such an increase in the degree of integration of a semiconductor device entails a reduction in a design rule, causing patterns of a semiconductor device to be reduced accordingly. Although an entire chip area may be increased in proportion to an increase in a memory capacity as semiconductor devices become super miniaturized and highly integrated, an area of a cell area where patterns of a semiconductor device are formed may be decreased. Accordingly, since a greater number of patterns are formed in a limited cell area in order to achieve a desired memory capacity, there is a need for formation of microscopic (fine) patterns having a reduced critical dimension.
A dynamic random access memory (DRAM) device includes a plurality of unit cells each having a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal (word line). The data transfer occurs by using a semiconductor property where electrical conductivity changes depending on doping characteristics. The transistor has three regions; a gate, a source, and a drain. Electric charges move between the source and the drain according to a control signal input to the gate of the transistor. The movement of the electric charges between the source and the drain is achieved through a channel region. The channel is doped to facilitate moving the charges.
In a typical method for manufacturing a transistor, a gate is formed in a semiconductor substrate, and a source and a drain are formed by doping impurities into both sides of the gate. In this case, a channel region of the transistor is defined between the source and the drain under the gate. A transistor having a horizontal channel region occupies a predetermined area of a semiconductor substrate. Therefore, for a given transistor, the number of memory cells may determine the size of the semiconductor device.
If the total area of the semiconductor memory device is reduced, the number of semiconductor memory devices per wafer is increased, thereby improving the productivity. Several methods for reducing the total area of the semiconductor memory device have been proposed. One method is to replace a conventional planar gate having a horizontal channel region with a recess gate in which a recess is formed in a substrate and a channel region is formed along a curved surface of the recess by forming a gate in the recess. Furthermore, a buried gate has been studied which can reduce parasitic capacitance of a bit line by burying the entire gate within the recess.
In a semiconductor device including a buried gate, a bit line contact plug is coupled to an active region of the semiconductor substrate which includes the buried gate. A method for forming a general bit line contact plug will hereinafter be described in detail.
An interlayer insulation film is formed over a semiconductor substrate including a buried gate, and the interlayer insulation film is etched to expose an active region so that a bit line contact hole is formed. In this case, a lower part of the bit line contact hole is formed to provide an interface sufficient to communicate with an active region. Subsequently, after a conductive layer is formed over the insulation film including a bit line contact hole, the conductive layer is etched back so that a bit line contact plug is formed.
However, during the etch-back process, the bit line contact plug may be etched so that it has a lower height than the interlayer insulation film, creating a step difference between the bit line contact plug and the surface of the interlayer insulation film. As a result, in a subsequent process for depositing a bit line barrier metal, an oxide material is rapidly generated between the bit line contact plug and the barrier metal. In addition, poor step coverage of the barrier metal may occur due to the step difference, and the bit line contact plug may be damaged when the bit line contact hole is small in size or is misaligned. As a result, resistance of the bit line contact plug is increased, resulting in an increase in the number of defective elements.